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fibre channel transmitter and receiver chipset technical data HDMP-1512 transmitter hdmp-1514 receiver features ? ansi x3.230-1994 fibre channel standard compatible (fc-0) ? selectable 531.25 mbaud or 1062.5 mbaud data rates ? selectable on chip laser driver and 50 w cable driver ? ttl compatible i/os ? single +5.0 v power supply applications ? mass storage system i/o channel ? work station/server i/o channel ? high speed peripheral interface description the HDMP-1512 transmitter and the hdmp-1514 receiver are bipolar integrated circuits, separately packaged, in 80 pin m- quad packages. they are used to build a high speed fibre channel link for point to point data com- munications. shown in figure 1 is a typical full duplex point-to- point fibre channel link. the sending system provides parallel, 8b/10b, encoded data and a transmit byte clock to the hdmp- 1512 transmitter. using the trans- mit byte clock, the transmitter converts the data to a serial stream and sends it over a copper cable or fiber-optic link. the receiver converts the serial data stream back to parallel encoded data and presents it, along with the recovered transmit byte clock, to the receiving system. the sending system has the option to electrically wrap the transmitted data back to the local receiver. it is possible to transmit over the cable driver, or laser driver when data is being wrapped back to the local receiver. the two-chip set (transmitter chip and receiver chip) is compatible with the fc-0 layer of the american national standards institute (ansi), fibre channel specification, x3.230-1994. this specification defines four standard rates of operation for fibre channel links. the hdmp- 1512 and hdmp-1514 chip-set will operate at the two highest defined serial rates of 531.25 mbaud and 1062.5 mbaud. these serial baud rates correspond to 8b/10b encoded byte rates of 50 mbytes/sec and 100 mbytes/sec respectively. the proper setting of a single pin on each chip selects the desired rate of operation. several features, exclusive to this chip-set, make it ideal for use in fibre channel links. in addition, the laser driver on the transmitter chip, the dual loss of light detectors on the receiver chip, and the power supervisor and power reset features make this chip-set ideal for use with laser optics. the serial cable driver (transmitter chip), and the cable equalizer (on the receiver chip), can be operated in conjunction with, or as an alternative to, the laser driver. the laser driver can also be driven directly with an external high speed serial input. altogether, the various features, input/output options, and flexibility of this chip-set make several unique link configurations possible. in particular, it is ideally suited for use in applications where conformance to the fcsi specification # 301-rev 1.0, gbaud link module specification, is desired.
2 figure 2. HDMP-1512 (tx) block diagram. ttl interface and input latch data byte 1 tx [10:19] ?si data byte 0 tx [00:09] frame multiplexer 10 10 20 i/o select cable drivers ?lout ?so pll/clock generator tbc laser driver internal clocks 2 2 ?lzout 2 laser controls ts2 ts1 ewrap ppsel spdsel -lzon fault -comgen transmitter operation the block diagram of the hdmp- 1512 transmitter is shown in figure 2. the basic functions of the transmitter chip are the ttl interface and input latch, frame multiplexing, input/output selection, cable drivers, laser driver, and monolithic phase locked loop clock generator. the actual operation of each function changes slightly, according to the desired configuration and option settings. figures 18 and 19 show schematically how to terminate each pin on the HDMP-1512 when used in systems incorporat- ing either copper or fiber media. there are two main modes of operation for the transmitter chip, both are based on the selected baud rate. the baud rate is controlled by the appropriate setting of the spdsel pin, #67. when this pin is set low, the transmitter operates at a serial rate of 531.25 mbaud. when pin #67 is set high the transmitter operates at a serial rate of 1062.5 mbaud. as such, the two main modes of operation are the 531.25 mbaud mode and the 1062.5 mbaud mode. the transmitter does not encode the applied data. it assumes the data is pre-encoded using the 8b/10b encoding scheme as defined in ansi x3.230-1994. the ttl input interface receives data at the standard ttl levels specified in the dc electrical specification table. the internal phase locked loop (pll) locks to the transmit byte clock, tbc. tbc is supplied to the transmitter chip by the sending system. tbc should be a 53.125 mhz clock ( 100 ppm) as defined in x3.230-1994. once the pll has locked to tbc, all the clocks used by the transmitter are generated by the internal clock generator. clock tx rx encoded data clock encoded data ref clock rx tx clock encoded data clock encoded data ref clock serial link serial link figure 1. point-to-point data link.
3 tions of 10 bit binary words, the 8b/10b code reserves 256 of them to represent the valid combinations of 8 bit data. some of the remaining combinations are reserved for special functions. the character reserved for defining the transmitted word boundary has been defined as the k28.5 character, also known as a comma character. the receiver will automatically reset registers and clock when it receives a comma character (this will be discussed in more detail in the receiver operation section). every valid 8 bit data word is actually represented by one of two 10 bit codes, indicating either positive or negative running disparity. the input latch only generates the k28.5 character with positive disparity (0011111010). in figure 2, the frame multiplexer utilizes shift registers and a multi-stage multiplexing scheme to convert the 10 or 20 parallel data bits to a serial data stream. this serial data stream is then fed directly into the input/ output select portion of the transmitter. the i/o select function allows use of both the internally serialized fibre channel data stream and an externally supplied fibre channel data stream denoted as si (pins 11 and 12). by using the proper settings of ts1, ts2, and ewrap (pins 76, 75, and 71 respectively), the internal data stream and the external data stream can be directed to various combinations of the cable driver output, the laser driver output, and the electrical loopback output. the possible i/o combinations are listed in the input output select table and the functionality is described in more detail in the transmitter laser driver operation section below. the cable driver function provides a 50 w differential cable driver output at pins 5 and 6 ( so). the simplified circuit is the o-bll section shown in figure 10. a similar output is provided to allow electrical loopback, or wrap of the local data back to the local receiver for diagnostics. this is denoted as lout on pin 8 and pin 9. the final function on the transmitter chip is the laser driver block which provides a high speed differential output, lzout, at pins 19 and 20. there are several other laser control i/os which will be HDMP-1512 input output select table data source for: active outputs mode ts1 ts2 ewrap so lzout lout so lzout lout 0 0 0 0 na internal na no yes no 1 0 0 1 na na internal no no yes 2 0 1 0 internal internal na yes yes no 3 0 1 1 internal na internal yes no yes 4 1 0 0 internal na na yes no no 5 1 0 1 na internal internal no yes yes 6 1 1 0 internal si na yes yes no 7 1 1 1 internal na si yes no yes when operating in the 531.25 mbaud mode, data byte 0, tx[00:09], is active and is clocked into the input latch a single byte (10 bits) on each rising edge of tbc. in the 1062.5 mbaud mode both data byte 0, tx[00:09], and data byte 1, tx[10:19], are active. in 1062.5 mbaud mode, data byte 0 and data byte 1 are clocked into the transmitter on the rising edge of every clock cycle, (tbc). there is one minor variation possible in the 1062.5 mbaud mode, referred to as ping-pong mode. ping- pong mode is selected by setting the ppsel pin (#34) high. in this mode the transmitter clocks data into the input latch one byte per half clock cycle. data byte 0 is transmitted on the rising edge of tbc and data byte 1 is trans- mitted 1/2 clock cycle later. see figure 16 for timing information. the input latch will stop sending the data applied to the tx[00:09] data pins when a low is applied to the -comgen pin (#32) and will send the pre-set special fibre channel character, k28.5 instead. the 8b/10b coding scheme, adopted by fibre channel, con- verts 8 bit data words into 10 bit representations of the actual data. of all the possible combina-
4 mux ?si 11 12 v cc _lz1 v cc _lz 23 24 gnd_lz 25 26 16 -lzon 30 lzpwron 36 laser on error detector fault 29 internal data stream input select ac amp disable window detector bandgap reference bandgap detector ac amp + 14 dc op-amp + 27 15 28 22 19 20 21 17 5 w v cc _lzac 0.1 ? 0.1 ? v cc +lzout -lzout lzcse 0.1 ? 25 w 5 w pot 2 50 w 0.1 ? v cc 0.1 ? 301 w 2.2 w 8 w p1 ( b >= 100) external control p2 25 w 0.1 ? 25 w transmission line pot 1 5 k w lzmdf lzbtp 0.1 ? v cc -lzbg lzdc 10 nf tx chip boundary 10 nf lztc figure 3. laser driver block diagram and external circuitry. described in more detail in the laser driver operation section below. transmitter laser driver operation the block diagram of the hdmp- 1512, tx, laser driver circuitry is shown in figure 3. the laser driver is enabled by setting -lzon (pin 30) low and lzpwron (pin 36) high. the circuitry in figure 3, shown outside the chip boundary (dotted box), illustrates the external components required to complete a typical laser driver connection. the input data source to the laser driver is user selected from either the internally generated data stream, or an externally supplied high speed data stream. the externally supplied data stream is applied to the high speed input si pins. the user selects between these two data sources through the proper settings of pins ts1, ts2, and ewrap (pins 76, 75, and 71). the possible combinations of active inputs and outputs are shown in the input/ output select table. the chosen high speed input is then modu- lated onto the laser by the ac amplifier. the external poten- tiometer, pot 2, shown connected to pin lzcse (# 14) is used to adjust the laser modulation depth. the laser driver output is at pins 19 and 20, lzout. laser diode dc bias control is provided through the lzdc (# 21) pin. adjustment of pot 1 sets the nominal dc bias desired for the laser diode. the equivalent output circuit of lzdc is shown in figure 4. laser diode fault and safety control is imple- mented through the combination v cc _lz lzdc 400 54 figure 4. lzdc equivalent output circuit (tx pin # 21). of the window detector, error detector, laser on pin # 30 (-lzon), laser monitor diode feedback pin # 22 (lzmdf), and the op-amp dc bias control circuit. the window detector monitors the voltage on pin lzmdf. if this voltage goes out of range by more than 10% from the nominal setting, the
5 figure 5. hdmp-1514 (receiver) block diagram. capacitor on pin lztc (# 27) will begin to discharge. after approximately 2 msec, the voltage on lztc falls to the fault value and the error detector will bring the fault pin (# 29) high to alert the system. the error detector will also hold the voltage on lzmdf low, until a reset is initiated. the -lzon pin is used to disable the laser driver under system control or in conjunction with an external open-fiber control (ofc) chip. this pin is also used to reset the error detector and recharge the capacitor on pin lztc. the lzpwron pin, # 36, is used to hold off dc power to the laser driver until proper dc bias is applied to the laser diode. when lzpwron goes high, the laser driver is enabled, when it is low, it is disabled. if not used, this pin should be tied low. receiver operation the block diagram of the hdmp- 1514 receiver is shown in figure 5. the functions included on the receiver are a coaxial cable equalizer, two independent loss of light (lol) detectors, an input select function, monolithic phase locked loop and clock recovery circuits, a clock generator, frame demultiplexer and comma detector, power supply super- visor, and output latch with ttl drivers. figures 20 and 21 show schematically how to terminate each pin on the hdmp-1514 when used in systems incorporat- ing either copper or fiber media. in the most basic sense, the receiver accepts a serial electrical data stream at 1062.5 mbaud or 531.25 mbaud and recovers the 8b/10b encoded parallel data and clock that was applied to the transmitter. like the transmitter, the receiver has several configu- ration options which interrelate according to the desired mode of operation. the two main modes of operation for the receiver are based on the desired signalling rate. the signalling rate is controlled by the proper setting of the spdsel pin # 71. when this pin is set low, the receiver operates at a serial rate of 531.25 mbaud. when pin # 71 is set high, the receiver operates at a serial rate of 1062.5 mbaud. in a typical configuration, the serial electrical data stream will be applied to the di pins, # 19 and # 20 on the receiver. the serial electrical data stream may have been transmitted over a fiber optic link or a copper cable link (several variations of each link type is possible). for use with copper links, a selectable cable equalizer is available at the input. this equalizer can be switched into or out of the data cable equalizer data byte 1 rx [10:19] l_unuse data byte 0 rx [00:09] 10 10 dr_ref -lck_ref -tclksel clkin ps_ct input select pll and clock select lol detectors supply supervisor clock generator output latch and ttl interface frame demux and comma detect lola lolb spdsel ?di -eqen -por rbc0 rbc1 com_det ppsel en_cdet ewrap 20 internal clocks v cc _hs ?lin
6 figure 6. simple circuit used to adjust the voltage on rx pin # 21, dr_ref. +5 v 2 k w 2 k w 8 k w potentiometer pin #21, dr_ref path using the -eqen pin, # 32. setting pin #32 high disables the equalizer. setting pin # 32 low enables the equalizer. the typical performance of the input equalizer is shown in the (frequency response) plot of figure 7. the impact of the equalizer is improved ber performance over long lengths of cable (10 to 20 meters). connected to the di input pins, prior to the equalizer, are the loss of light detectors, lola (pin 28) and lolb (pin 29). actually, since these detectors monitor the incoming serial electrical data stream, they can be thought of as loss of signal detectors. these signals can be used to determine if the incoming signal line is connected properly. in the case of a fiber optic system they can be used to shut down laser output power for laser safety considera- tions. the lol detectors measure transitions in the incoming data stream that exceed a pre-set peak-to-peak differential signal or threshold level. the default peak- to-peak differential threshold voltage is 25 mv and can be adjusted by connecting a resistive divider to the dr_ref pin (#21) as shown in figure 6. the rela- tionship of the dr_ref voltage to the peak-to-peak differential threshold voltage is shown in figure 8. when the input signal level falls below the threshold voltage for 4 clock cycles, or 80 bit times, the signals at pins 28 and 29 will go high. once the serial data stream passes the cable equalizer function it is directed to an input select section. a second high speed serial data input, denoted lin, is applied at pins # 16 and # 17 and is connected directly to the input select section. this data input is intended for diagnostic purposes. it is not affected by the cable equalizer and has no effect on the loss of light detectors. the lin input should mainly be used when it is desired to directly connect the local transmitter serial output data stream to the local receiver (local loopback). the input select function uses the ewrap signal, pin # 34, to determine which serial data stream to pass on to the rest of the receiver. if ewrap is high, then the lin signal is used. if ewrap is low the di signal is used. the pll and clock select circuitry contains a monolithic, tunable, oscillator. this oscillator phase locks to the selected high speed data input and recovers the high speed serial clock. to keep the internal oscillator tuned close to the incoming signal frequency, an external reference oscillator is applied to the clkin input, pin # 7. the signal on the -lck_ref input, pin # 36, controls whether the receiver oscillator locks to the reference oscillator or to the incoming data stream. when -lck_ref is toggled low, the receiver frequency locks to the signal at clkin. when the -lck_ref pin is toggled high, the receiver phase locks to the selected high speed serial data input. this process of locking to a local reference oscillator, prior to receiving incoming data, improves (shortens) the overall time required by the receiver to acquire lock. the lunuse input, pin 73 will cause the receiver to frequency lock on the clkin signal under faulty or no input signal conditions. the lunuse signal needs to be provided to the receiver by an external open fiber control circuit or other control logic. once the receiver has locked to the incoming data stream at di (ewrap = 0 and -lckref = 1), if lunuse toggles high then the receiver will switch to frequency lock on clkin. if, however, the receiver is locked onto the local data wrapped back to the li input (ewrap = 1 and -lckref = 1) then the receiver stays locked to the incoming signal at li even when lunuse goes high. in summary, when the lunuse input is set low, the receiver frequency locks to the clkin signal when the input to -lckref is low and phase locks to either the di or li signal, depending on which input is selected, when -lckref toggles high. lunuse then, is used to cause the receiver to frequency lock to the reference oscillator at clkin after the receiver has established phase lock to the incoming data signal at di, and the system determines the link is faulty and not in ewrap mode.
7 -lck_ref ewrap lunuse rx lock 0 x x clkin 100di 1 0 1 clkin 111li 110li the table above llustrates these various settings. normally, the recovered serial clock is used by the clock gener- ator to generate the various internal clocks the receiver uses including the receive clock outputs rbc0 (pin 69) and rbc1 (pin 67). the final receiver clocking feature is included for test purposes only. by applying a low to the -tclksel input, pin 5, the internal phase locked loop is bypassed and the receiver uses the clkin signal as the high speed serial clock. under normal operating conditions the -tclksel pin should be tied high. in a fibre channel link, frame alignment is accomplished through the transmission and detection of the special character k28.5, also known as a comma character. prior to actual data transmission the system will transmit a comma character over the physical link. to start, the receiver should be frequency locked to the local reference oscillator (-lckref set low). to ensure frequency lock is achieved, -lckref should be held low for a minimum of 500 m sec (see rx timing characteris- tics, t flock ). it then should be toggled high. at this point the receiver will phase lock to the incoming data stream at the di input but the actual frame or word boundary will be undeter- mined. the en_cdet pin (# 38) should be set high now. with the en_cdet pin set high, the receiver will scan the incoming data stream for a comma charac- ter. once a comma character is received, the internal clocks and registers are reset giving proper frame alignment. the receiver will reset on every comma character that is transmitted as long as en_cdet is held high. when the internal clock genera- tor is reset due to the detection of a comma character, internal circuitry prevents a clock sliver from appearing at the receive clock outputs (rbc0 and rbc1). this antisliver circuit assures each clock output high, or low, will be held for at least one half the frame rate time. when en_cdet is set low the receiver ignores all incoming comma characters and assumes the current frame and bit alignment is correct. en_cdet is automatically disabled when -lckref is set low. the com_det pin, #75, on the receiver will go high when a comma character is detected (see figure 15). now that frame alignment has been achieved, the receiver is ready to receive full speed serial data and demultiplex it back to its original 10 bit or 20 bit relative gain ?db 1.00e + 06 -10 frequency ?f ?hz 1.00e + 08 4 0 -4 -6 -8 1.00e + 07 1.00e + 10 2 -2 1.00e + 09 figure 7. typical frequency response plot of the internal input equalizer. parallel word format. this data is then placed into the output latch. the data output is presented in the standard ttl output levels and characteristics specified in the dc and ac electrical specifica- tion tables. when operating in 531 mbaud mode the receiver generates output data in a single byte wide (10 bits) output format. this is data byte 0 and is denoted rx[00:09] on pins 53 through 62. in 1063 mbaud mode the data output is generated in a two byte wide (20 bits) format, data byte 0 and data byte 1. data byte 0 is denoted rx[00:09] on pins 53 through 62 and data byte 1 is denoted rx[10:19] on pins 43 through 52. in standard operation data byte 0 and data byte 1 will both be clocked into the output latch at the same time, on the falling edge of rbc0. an alternate mode of operation is ping-pong mode. in ping-pong mode the data is clocked out 1 byte at a time with byte 0 clocked out on the falling edge of rbc0 and byte 1 clocked out on the falling edge of rbc1. to set the receiver to operate in ping-pong mode, the ppsel pin, # 76, should be set high (otherwise it should be tied low).
8 HDMP-1512 (tx), hdmp-1514 (rx) specified operating rates t c = 0 c to +85 c, v cc = 4.5 v to 5.5 v transmit byte clock (tbc) serial baud rate (mhz) (mbaud/sec) spdsel min. max. min. max. 0 52.0 54.0 520 540 1 52.0 54.0 1040 1080 HDMP-1512 (tx), hdmp-1514 (rx) absolute maximum ratings operation in excess of any one of these conditions may result in permanent damage. symbol parameter units min. max. v cc supply voltage v -0.5 6.0 v in,ttl ttl input voltage v -0.7 v cc + 0.7 v in,h50 i-h50 input voltage, figure 9 v v cc - 2.0 v cc + 0.7 i o,ttl ttl output source current ma 13 t stg storage temperature c -40 +130 t j junction operating temperature c 0 +130 t max maximum assembly temperature (for 10 seconds c 0 +260 maximum) recommended handling precautions additional circuitry is built into the various input and output pins on these chips to protect them against low level electrostatic discharge, however, they are still esd sensitive and standard procedures for static sensitive devices should be used in the handling and assembly of the HDMP-1512 and the hdmp-1514. the packing materials used for shipment of these devices was selected to provide esd protection and to prevent mechanical damage. during test and use, under power- up conditions, extreme care should be taken to prevent the high speed i/os from being connected to ground as permanent damage to the device is likely. rx power supply supervisor a power supply supervisor feature has been designed into the receiver as a system aid during power-up. the -por (pin # 27) output is held low until the power supply voltage (v cc ) crosses the nominal threshold of 4.25 volts. then, following a delay time determined by the capacitor value connected to the ps_ct pin (# 22), the -por output goes high. the typical delay time is 8 msec, with a 0.47 m f capacitor attached to ps_ct. lol threshold voltage p-p differential ?mv 0 0 dr_ref voltage ?v 1.0 90 60 40 20 10 0.5 2.5 80 50 1.5 2.0 70 30 default threshold figure 8. typical plot of loss of light threshold voltage vs. dr_ref voltage.
9 HDMP-1512 (tx), hdmp-1514 (rx) transmitter & receiver byte rate clock requirements t c = 0 c to +85 c, v cc = 4.5 v to 5.5 v symbol parameter unit min. typ. max. f nominal frequency mhz 53.120 53.125 53.130 f tol frequency tolerance (for fibre channel compliance) ppm -100 +100 symm symmetry (duty cycle) % 40 60 HDMP-1512 (tx), hdmp-1514 (rx) ac electrical specifications t c = 0 c to +85 c, v cc = 4.5 v to 5.5 v, unless otherwise specified symbol parameter units min. typ. max. t r,ttlin input ttl rise time, 20% to 80% nsec 2 t f,ttlin input ttl fall time, 20% to 80% nsec 2 t r,ttlout output ttl rise time, 20% to 80%, 15 pf load nsec 2 4 t f,ttlout output ttl fall time, 20% to 80%, 15 pf load nsec 2 4 t r, bll bll rise time, ac coupled, 50 w source and load, psec 150 350 20% to 80% t f,bll bll fall time, ac coupled, 50 w source and load, psec 150 350 20% to 80% vswr i,h50 h50 input vswr, ac coupled, 50 w source and load 2.0 vswr o,bll bll output vswr, ac coupled, 50 w source and load 2.0 v ip,h50 h50 input peak-to-peak differential voltage, ac coupled, mv 50 1200 2000 50 w source lol th loss of light threshold, peak-to-peak, differential, mv 13 25 40 t c = 60 c, v cc = 5.0 v v op,bll bll output peak-to-peak differential voltage, mv 1200 1400 ac coupled, 50 w load ps dt power supervisor delay time, with ps_ct terminated in msec 15 0.47 m f HDMP-1512 (tx) output jitter characteristics t c = 0 c to +85 c, v cc = 4.5 v to 5.5 v symbol parameter units min. typ. max. rj rms random jitter at so, the high speed electrical data port psec 10 dj rms deterministic jitter at so, the high speed electrical psec 22 data port
10 HDMP-1512 (tx), hdmp-1514 (rx) dc electrical specifications t c = 0 c to +85 c, v cc = 4.5 v to 5.5 v symbol parameter unit min. typ. max. v ih,ttl ttl input high voltage level, guaranteed high signal for v 2 5 all inputs, i ih = 100 m a v il,ttl ttl input low voltage level, guaranteed low signal for all v 0 0.8 inputs, i il = -1ma v oh,ttl ttl output high voltage level, i oh = 1 ma v 2.4 5 v ol,ttl ttl output low voltage level, i ol = -1 ma v 0 0.6 i cc,tx transmitter v cc supply current, without laser biased ma 320 450 i cc,rx receiver v cc supply current, with ttl output data 50% 1s ma 400 550 ps th power supervisor dc threshold voltage v 4.0 4.25 4.5 HDMP-1512 (tx) laser driver characteristics t c = 0 c to +85 c, v cc = 4.5 v to 5.5 v symbol parameter units min. typ. max. i pb laser diode prebias current set range (using ma 20 130 external pnp transistor, p1 in figure 3, with b > 100) i mod laser diode modulation current set range ma 25 (peak to peak) into 25 w load t r,lzout laser driver rise time, 25 w load, 20% to 80% psec 325 t f,lzout laser driver fall time, 25 w load, 20% to 80% psec 325 t lztc time for v lztc to discharge to fault threshold msec 2 when terminated with c = 0.1 m f v lzcse lzcse reference voltage v 0.4 v lzbtp bandgap test point reference voltage v 2.3 v lzmdf laser monitor diode feedback voltage v 1.85 a dcoa laser driver dc operational amplifier gain, db 35 unloaded, see figure 3 f -3db laser driver dc operational amplifier bandwidth mhz 300 v lzdc_op recommended lzdc operating range, laser diode v v cc - 1.8 v cc - 0.75 dc bias control v lzdc_dcl lzdc laser dc bias low voltage setting v v cc - 2.0 v lzdc_dch lzdc laser dc bias high voltage setting v v cc - 0.6 i lzdc_l lzdc load current, over v lzdc_op ma 1.3 z lzdc_aco lzdc ac output impedance w 400 z lzmdf_aci lzmdf ac input impedance w 10,000 i lzmdf lzmdf input current m a615
11 HDMP-1512 (tx) timing characteristics t c = 0 c to +85 c, v cc = 4.5 v to 5.5 v, ppsel = 0, spdsel = 1 symbol parameter units min. typ. max. t s setup time nsec 2 t h hold time nsec 2.3 t_txlat transmit lateny [1] nsec 18 note: 1. the transmitter latency is defined as the delay time from when a valid data word at tx[00:19] is clocked into the transmitter (triggered by the rising edge of tbc during the time t h ) and when the first serial bit is transmitted on pins so (defined by the leading edge of the first bit transmitted). hdmp-1514 (rx) timing characteristics t c = 0 c to +85 c, v cc = 4.5 v to 5.5 v, ppsel = 0, spdsel = 1 symbol parameter units min. typ. max. t flock frequency lock rate, loop filter capacitor = 0.01 m f khz/ m sec 100 blt bit lock time bit times 2500 t s setup time nsec 2.5 t h hold time nsec 6.0 t s setup time for data rx[10:19] in ping-pong mode nsec 6 t h hold time for data rx[10:19] in ping-pong mode nsec 8 t_rxlat receive latency [1] nsec 38 note: 1. the receiver latency is defined as the delay time from receiving the first serial bit of a parallel data word (defined by the rising edge of the first bit received at pins di), and when that word is first clocked out at rx[00:19] (as defined by the falling edge of rbc0 or rbc1, following time t s ). HDMP-1512 (tx), hdmp-1514 (rx) thermal characteristics, t c = 0 c to +85 c symbol parameter units typ. p d, tx transmitter power dissipation, v cc = +5 v watt 1.6 p d, rx receiver power dissipation, v cc = +5 v watt 2 q jc thermal resistance, junction to case c/watt 12 i/o type definitions i/o type definition i-ttl input ttl. floats high when left open. o-ttl output ttl. o-bll 50 w buffer line logic output driver. should be ac coupled to drive 50 w loads. it can also drive the i-h50 inputs through differential direct coupling. note: all unused outputs should be terminated with 50 w to v cc . i-h50 input with internal 50 w terminations. input is diode level shifted so that it can swing around v cc . can be driven with single-ended or differential, ac coupled configuration. to avoid permanent damage, these inputs should not be connected to ground. c external circuit node. s power supply or ground.
12 figure 10. o-bll and i-h50 simplified circuit schematics. (note: i-h50 inputs should never be connected to ground as permanent damage to the device may result.) v cc _log esd gnd_log gnd_hs v cc _hs 80 80 o-bll i-h50 esd esd esd v cc _log esd gnd_log gnd_hs v cc _hs esd esd esd 50 50 v cc _hs 0.1 ? 0.1 ? zo = 50 w zo = 50 w figure 9. o-ttl and i-ttl simplified circuit schematic. v cc _ttl 10 k v bb 1.4 v 10 k v cc _log esd esd gnd_ttl gnd_log v cc _log esd esd gnd_log gnd_ttl v cc _ttl 6 k 36 72 800 o_ttl i_ttl
13 HDMP-1512 (tx), pin assignments pin name pin name pin name pin name 01 cap1a 21 lzdc 41 vcc_ttl 61 tx[18] 02 cap1b 22 lzmdf 42 vcc_ttl 62 tx[19] 03 gnd_a 23 vcc_lz 43 tx[00] 63 vcc_ttl 04 gnd_a 24 vcc_lz 44 tx[01] 64 vcc_ttl 05 +so 25 gnd_lz 45 tx[02] 65 gnd_ttl 06 -so 26 gnd_lz 46 tx[03] 66 gnd_ttl 07 vcc_hs1 27 lztc 47 tx[04] 67 spdsel 08 +lout 28 lzbtp 48 tx[05] 68 vcc_log 09 -lout 29 fault 49 tx[06] 69 -eclksel 10 gnd_lzhs 30 -lzon 50 tx[07] 70 gnd_log 11 +si 31 gnd_log 51 tx[08] 71 ewrap 12 -si 32 -comgen 52 tx[09] 72 vcc_log 13 vcc_hs2 33 vcc_log 53 tx[10] 73 tbc 14 lzcse 34 ppsel 54 tx[11] 74 gnd_log 15 vcc_lzbg 35 gnd_log 55 tx[12] 75 ts2 16 vcc_lz1 36 lzpwron 56 tx[13] 76 ts1 17 vcc_lzac 37 vcc_log 57 tx[14] 77 vcc_a 18 gnd_lzhs 38 nc 58 tx[15] 78 vcc_a 19 +lzout 39 gnd_ttl 59 tx[16] 79 cap0a 20 -lzout 40 gnd_ttl 60 tx[17] 80 cap0b gnd_ttl gnd_ttl nc v cc _log lzpwron gnd_log ppsel v cc _log -comgen gnd_log -lzon fault lzbtp lztc gnd_lz gnd_lz gnd_ttl gnd_ttl spdsel v cc _log -eclksel gnd_log ewrap v cc _log tbc gnd_log ts2 ts1 v cc _a v cc _a cap0a cap0b 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v cc _ttl v cc _ttl tx[19] tx[18] tx[17] tx[16] tx[15] tx[14] tx[13] tx[12] tx[11] tx[10] tx[09] tx[08] tx[07] tx[06] tx[05] tx[04] tx[03] tx[02] tx[01] tx[00] v cc _ttl v cc _ttl cap1a cap1b gnd_a gnd_a +so -so v cc _hs1 + lout - lout gnd_lzhs +si -si v cc _hs2 lzcse v cc _lzbg v cc _lz1 v cc _lzac gnd_lzhs +lzout -lzout lzdc lzmdf v cc _lz v cc _lz HDMP-1512 top view figure 11. HDMP-1512 (tx) package layout, top view.
14 HDMP-1512 (tx), signal definitions symbol signal name i/o logic type description cap0[a:b] loop filter capacitor c pll filter capacitor should be connected from pins pins [79,80] 79 and 80 to pins 1 and 2 (typical value = 0.01 m f). see figures 18, 19, 20, and 21. cap1[a:b] loop filter capacitor c pll filter capacitor should be connected from pins pins [1,2] 79 and 80 to pins 1 and 2 (typical value = 0.01 m f). see figures 18, 19, 20, and 21. -comgen comma generate input ttl an active low input, causes the transmitter to pin [32] internally generate the positive disparity k28.5 byte (0011111010) for transmission. -eclksel external clock select input ttl an active low input, selects the tbc inputs to be used pin [69] as the serial clock, bypassing the pll. used mainly for testing. ewrap enable wrap input ttl works in conjunction with ts1 and ts2 to specify pin [71] input and output ports. fault laser fault indicator output ttl indicates the laser output level has moved outside of pin [29] the window detector set boundary and the laser test capacitor (lztc) has discharged to a fault level. this output is reset by the -lzon pin. gnd_a analog ground s normally 0 volts. used to provide a clean ground plane pins [3,4] for the critical pll and high speed analog cells. gnd_log logic ground s normally 0 volts. used for all internal pecl logic. pins [31,35,70,74] should be completely isolated from the noisy ttl ground. gnd_lz laser ground s normally 0 volts. used for all laser circuitry. pins [25,26] gnd_lzhs laser high speed s normally 0 volts. ground pins [10,18] gnd_ttl ttl ground s normally 0 volts. used for all ttl i/o buffer cells. pins [39,40,65,66] lout local serial data output bll high speed data port, typically connected to the lin pins [8,9] port on the local receiver during serial wrap mode. lzbtp laser bandgap test c this pin is internally set to 2.3 vdc and normally point should connect to one terminal of the laser dc bias pin [28] resistor (pot1 figure 3). lzcse laser current source c used to set the bias current of the ac laser driver. emitter typical use is shown in figure 3 where pot2 is used to pin [14] set the laser modulation depth. lzdc laser dc drive c used to control the laser diode dc bias (figure 3). pin [21] lzout laser driver serial c ac driver to the laser diode. the outputs should be ac output coupled to the laser bias circuit. pins [19,20] lzmdf laser monitor diode c connects to the laser monitor diode and one terminal of feedback the laser dc bias resistor (pot1). under normal pin [22] operating conditions, the voltage on this pin will be 1.85 v. -lzon laser control and input ttl the laser diode is turned on (active low) or off (high) reset with this input. in the off state the capacitor on pin pin [30] lztc charges, resetting the window detector (figure 3).
15 HDMP-1512 (tx), signal definitions (contd.) symbol signal name i/o logic type description lzpwron laser power on input ttl used in conjunction with the dual loss of light pin [36] detectors and the ofc circuit to assure the system is ready to power up the laser. lztc laser timing cap c the capacitor connected to this pin will be pre- pin [27] charged at power-up. during operation, if the window detector detects the laser bias to be out of range, this capacitor will begin to discharge. if the condition lasts long enough, the capacitor voltage will fall below the fault level and the fault pin will go high. nominal fault level is <1.0 volts. ppsel ping-pong select input ttl a high signal applied to this pin causes the transmitter pin [34] to clock the data in by alternating between data byte 0 on the rising edge of tbc and data byte 1 one half clock cycle later. when this pin is low, both data bytes are clocked in on the rising edge of tbc. si laser external serial input h50 the signal on this pin is input directly to the internal input laser driver circuitry or the lout pin. this input is pins [11,12] selected with the proper setting of ts1, ts2 and ewrap (see input/output select table). so cable serial data output bll high speed data output port. see input/output select output table to enable this output. pins [5,6] spdsel serial speed select input ttl sets the chip to operate at the serial data rate of 1062.5 pin [67] mbaud (high) or 531.25 mbaud (low). tbc transmit byte clock input ttl a 53.125 mhz clock supplied by the host system. this pin [73] reference clock is multiplied by 10 or 20 to generate the serial bit clock (531.25 mhz or 1062.5 mhz). ts[1:2] input/output select input ttl ts1 and ts2 work in conjunction with ewrap to input specify active input and output ports. pins [75,76] tx[00.19] data inputs input ttl two, 10 bit, pre-encoded data bytes. byte 0 is pins [43:62] comprised of bits tx[00:09] and byte 1 is comprised of bits tx[10:19]. the serialized bit stream is transmitted tx[00] through tx[09] then tx[10] through tx[19]. vcc_a analog supply s provides a clean power source for the critical pll pins [77, 78] and high speed analog cells. normally +5.0 volts. vcc_hs1 high speed supply 1 s provides a clean power source for the high speed pin [7] cells. noise on this line should be minimized for best performance. normally +5.0 volts. vcc_hs2 high speed supply 2 s provides a clean power source for the high speed pin [13] cells. noise on this line should be minimized for best performance. normally +5.0 volts. vcc_log logic power supply s used for all internal pecl logic. isolate from the pins [33,37,68,72] noisy ttl supply. normally +5.0 volts. vcc_lz laser power supply s power supply for low speed laser driver circuitry. pins [23,24] normally +5.0 volts. vcc_lz1 laser power supply s power supply for all laser driver ac circuitry. pin [16] normally +5.0 volts.
16 HDMP-1512 (tx), signal definitions (contd.) symbol signal name i/o logic type description vcc_lzac laser power supply s power supply for all high speed laser driver circuitry. pin [17] normally +5.0 volts. vcc_lzbg laser power supply s power supply for low speed laser driver circuitry. pins [15] normally +5.0 volts. vcc_ttl ttl power supply s power supply for all ttl buffer i/o cells. normally pins [41,42,63,64] +5.0 volts. nc pin [38] no connection. figure 12. hdmp-1514 (rx) package layout. gnd_ttl gnd_ttl en_cdet v cc _log -lck_ref gnd_log ewrap v cc _log -eqen gnd_log nc lolb lola por gnd_hs gnd_hs gnd_ttl gnd_ttl rbc[1] v cc _log rbc[0] gnd_log spdsel v cc _log l_unuse gnd_log com_det ppsel v cc _a v cc _a cap0a cap0b 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v cc _ttl v cc _ttl rx[00] rx[01] rx[02] rx[03] rx[04] rx[05] rx[06] rx[07] rx[08] rx[09] rx[10] rx[11] rx[12] rx[13] rx[14] rx[15] rx[16] rx[17] rx[18] rx[19] v cc _ttl v cc _ttl cap1a cap1b gnd_a gnd_a -tclksel n_rxtemp clkin (& tclk) p_rxtemp gnd_ttla v cc _ttla nc nc v cc _hs gnd_hs v cc _hs2 -lin +lin v cc _hs2 -di +di dr_ref ps_ct v cc _hs v cc _hs hdmp-1514 top view
17 hdmp-1514 (rx), pin assignments pin name pin name pin name pin name 01 cap1a 21 dr_ref 41 vcc_ttl 61 rx[01] 02 cap1b 22 ps_ct 42 vcc_ttl 62 rx[00] 03 gnd_a 23 vcc_hs 43 rx[19] 63 vcc_ttl 04 gnd_a 24 vcc_hs 44 rx[18] 64 vcc_ttl 05 -tclksel 25 gnd_hs 45 rx[17] 65 gnd_ttl 06 n_rxtemp 26 gnd_hs 46 rx[16] 66 gnd_ttl 07 clkin (tclk) 27 -por 47 rx[15] 67 rbc[1] 08 p_rxtemp 28 lola 48 rx[14] 68 vcc_log 09 gnd_ttla 29 lolb 49 rx[13] 69 rbc[0] 10 vcc_ttla 30 nc 50 rx[12] 70 gnd_log 11 nc 31 gnd_log 51 rx[11] 71 spdsel 12 nc 32 -eqen 52 rx[10] 72 vcc_log 13 vcc_hs 33 vcc_log 53 rx[09] 73 l_unuse 14 gnd_hs 34 ewrap 54 rx[08] 74 gnd_log 15 vcc_hs2 35 gnd_log 55 rx[07] 75 com_det 16 -lin 36 -lck_ref 56 rx[06] 76 ppsel 17 +lin 37 vcc_log 57 rx[05] 77 vcc_a 18 vcc_hs2 38 en_cdet 58 rx[04] 78 vcc_a 19 -di 39 gnd_ttl 59 rx[03] 79 cap0a 20 +di 40 gnd_ttl 60 rx[02] 80 cap0b hdmp-1514 (rx), signal definitions symbol signal name i/o logic type description cap0[a:b] loop filter capacitor c pll filter capacitor should be connected from pins pins [79,80] 79 and 80 to pins 1 and 2 (typical value = 0.01 m f). see figures 18, 19, 20, and 21. cap1[a:b] loop filter capacitor c pll filter capacitor should be connected from pins pins [1,2] 79 and 80 to pins 1 and 2 (typical value = 0.01 m f). see figures 18, 19, 20, and 21. clkin receive reference input ttl a 53.125 mhz clock supplied by the host system. (tclk) clock clkin is used by the internal pll to acquire frequency pin [7] lock when the -lckref input is brought low. com_det comma detect output ttl indicates the detection of a comma character pin [75] (k28.5 of positive disparity). it is only active when en_cdet is high. di serial data inputs input h50 high speed serial data inputs, selected when ewrap pins [19,20] is set low. an optional cable equalizer may also be enabled, see eqen.
18 hdmp-1514 (rx), signal definitions (contd.) symbol signal name i/o logic type description dr_ref receiver reference c this node is used to set the peak-to-peak signal level pin [21] of the loss of light detection circuitry. en_cdet enable comma detect input ttl when high, the receiver will reset internal clocks and pin [38] registers when an incoming comma character (k28.5) of positive disparity (0011111xxx) is detected. when low, clocks and registers will not reset and the comma detect output is disabled. comma detect is also disabled whenever -lck_ref is set low. -eqen equalizer enable input input ttl when set low, the internal cable equalizer amplifier on pin [32] the di lines is enabled. ewrap enable wrap input ttl when set high, the high speed data is taken from the pin [71] lin port, enabling the data input from the local transmitter. when this input is set low, the high speed input is taken from the di lines. gnd_a analog ground s normally 0 volts. used to provide a clean ground plane pins [3,4] for the critical pll and high speed analog cells. gnd_hs high speed ground s normally 0 volts. pins [14,25,26] gnd_log logic ground s normally 0 volts. used for all internal pecl logic. pins[31,35,70,74] should be completely isolated from the noisy ttl ground. gnd_ttl ttl ground s normally 0 volts. used for all ttl i/o buffer cells. pins [39,40,65,66] gnd_ttla ttl ground s normally 0 volts. pin [9] -lck_ref lock to reference input ttl a low input causes the internal pll to acquire pin [36] frequency lock on the external reference signal applied at clkin. to assure lock, this pin should be held low for at least 500 m sec and held high at all other times. a low input disables the comma detect function. l_unuse link unusable input ttl typically supplied from open fiber control circuitry. pin [73] used in conjunction with ewrap and -lck_ref to keep the internal vco near operational frequency, optimizing frequency lock times. lin local serial data input h50 high speed data port, typically connected to the lout pins [16,17] port on the local transmitter when in serial wrap mode. lola loss of light output ttl a high signal on this pin indicates the amplitude of signal the input serial data has fallen below a preset level pin [28] (see dr_ref) or no transitions have been detected within 4 cycles of tbc. lolb loss of light output ttl a high signal on this pin indicates the amplitude of signal the input serial data has fallen below a preset level pin [29] (see dr_ref) or no transitions have been detected within 4 cycles of tbc. n_rxtemp temperature monitor c used in conjunction with pin 8 (p_rxtemp) to pin [6] monitor the on-chip temperature diode (cathode.) p_rxtemp temperature monitor c used in conjunction with pin 6 (n_rxtemp) to pin [8] monitor the on-chip temperature diode (anode.) -por power on reset output ttl active low output. monitors the power supply voltage pin [27] on startup to assure v cc is at the proper dc level.
19 hdmp-1514 (rx), signal definitions (contd.) symbol signal name i/o logic type description ppsel ping-pong select input ttl a high input instructs the receiver to clock the data pin [76] out in ping-pong mode. byte 0 will be clocked out on the falling edge of rbc0 and byte 1 will be clocked out on the falling edge of rbc1. a low input instructs the receiver to clock both data bytes out on the falling edge of rbc0. ps_ct power supply timing c pin for connecting the timing capacitor for the power cap supervisor circuit. pin [22] rbc[0:1] receive byte clocks output ttl two clocks, 180 out of phase, generated from the pin [67, 69] recovered data. used to clock out the two 10 bit data bytes. rx[00:19] data outputs output ttl two, 10 bit, bytes. byte 0 is comprised of bits pins [43, 62] rx[00:09] and byte 1 is comprised of bits rx[10:19]. the serialized bit stream is received tx[00] through tx[09] then tx[10] through tx[19]. spdsel serial speed select input ttl sets the chip to operate at the serial data rate of 1062.5 pin [71] mbaud (high) or 531.25 mbaud (low). -tclksel test clock select input ttl an applied low selects clkin as the serial/bit-rate clock pin [5] and bypasses the internal pll. used for testing only. vcc_a analog supply s provides a clean power source for the critical pll pins [77, 78] and high speed analog cells. normally +5.0 volts. vcc_hs1 high speed supply s provides a clean power source for the high speed pins [13,23,24] receiver cell i-h50. noise on this line should be minimized for best performance. normally +5.0 volts. vcc_hs2 high speed supply 2 s provides a clean power source for the high speed pins [15,18] receiver cell i-h50. noise on this line should be minimized for best performance. normally +5.0 volts. vcc_log logic power supply s used for all internal pecl logic. isolate from the pins [33,37,68,72] noisy ttl supply. normally +5.0 volts. vcc_ttl ttl power supply s power supply for all ttl buffer i/o cells. normally pins [41,42,63,64] +5.0 volts. vcc_ttla ttl power supply s power supply for all ttl i/o buffer cells. normally pin [10] +5.0 volts. nc pins [11,12,30] no connection.
20 package description and assembly recommendations the HDMP-1512 and hdmp- 1514 are available in the industry standard m-quad 80 lead package. the outline dimensions conform to jedec plastic qfp specifications and are shown in figure 13. the package material is aluminum. to facilitate surface mounting, the leads have been formed into a gullwing config- uration. we recommend keeping the package temperature, t c , below 85 c. forced air cooling may be required. m-quad 80 package specifications item specification package material aluminum lead finish material 85/15 sn/pb lead finish thickness 300-600 m inches lead coplanarity 0.004 inches maximum figure 13. HDMP-1512 and hdmp-1514 package outline. 19.786 + 0.18 - 0.08 ( 0.779 ) + 0.008 - 0.002 23.20 ?0.10 (0.913 ?0.004) top view pin #1 id 13.792 + 0.16 - 0.04 ( 0.543 ) + 0.008 - 0.002 17.20 ?0.10 (0.677 ?0.004) 0.35 (0.014 ) 0.15 (0.006) 0.80 ?0.13 (0.031 ?0.005) 2.64 ?0.13 (0.104 ?0.005) 0.38 ?0.05 (0.015 ?0.002) 7 typ. 0.80 (0.0315 ) typ. all dimensions are in millimeters (inches).
21 figure 14. HDMP-1512 (transmitter) timing diagram, with ppsel = 0. figure 15. hdmp-1514 (receiver) timing diagram, with ppsel = 0. ts th k28.5 data data rx[00:19] rbco ts th 18.8 ns com_det ts tbc th data data data data data tx[00:19]
22 figure 17. hdmp-1514 (receiver) timing diagram in ping-pong mode, with ppsel = 1. ts tbc th data data data data data tx[00:09] ts th data data data data tx[10:19] 1/2 clock cycle (tbc) figure 16. HDMP-1512 (transmitter) timing diagram in ping-pong mode, ppsel = 1. data data data rx[10:19] rbc1 ts th 18.8 ns ts' th' data data rx[00:09] rbc0 ts' th' 18.8 ns com_det k28.5
23 figure 18. typical transmitter pin terminations for applications requiring high speed serial copper drivers ( so). laser driver outputs are disabled. for 1062.5 mbd operation only, spdsel (pin 67) set high, non ping-pong mode (ppsel = 0). 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 +5.0 v tx[19] tx[18] tx[17] tx[16] tx[15] tx[14] tx[13] tx[12] tx[11] tx[10] tx[09] tx[08] tx[07] tx[06] tx[05] tx[04] tx[03] tx[02] tx[01] tx[00] +so -so + lout - lout +si -si nc nc nc nc nc HDMP-1512 top view 0.1 ? 0.01 ? 0.1 ? 0.1 ? 0.1 ? nc nc nc nc +5.0 v ewrap tbc +5.0 v +5.0 v
24 figure 19. typical transmitter pin terminations for applications using the on-chip laser driver. for details of the laser driver connections, indicated by *, see figure 3 on page 4. for 1062.5 mbd operation only, spdsel (pin 67) set high, non ping-pong mode (ppsel = 0). 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 +5.0 v tx[19] tx[18] tx[17] tx[16] tx[15] tx[14] tx[13] tx[12] tx[11] tx[10] tx[09] tx[08] tx[07] tx[06] tx[05] tx[04] tx[03] tx[02] tx[01] tx[00] +so -so + lout - lout +si -si lzcse* +lzout* -lzout* lzdc* lzmdf* HDMP-1512 top view 0.01 ? 0.1 ? 0.1 ? 0.1 ? fault* lzbtp* lztc* nc +5.0 v ewrap tbc +5.0 v ts1,2 v cc _lzac* +5.0 v 0.1 ? -lzon* lzpwron*
25 figure 20. typical receiver pin terminations for applications using high speed serial copper links ( din). for 1062.5 mbd operation only, spdsel (pin 71) set high, non ping-pong mode (ppsel = 0). 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 +5.0 v rx[00] rx[01] rx[02] rx[03] rx[04] rx[05] rx[06] rx[07] rx[08] rx[09] rx[10] rx[11] rx[12] rx[13] rx[14] rx[15] rx[16] rx[17] rx[18] rx[19] refclk nc nc -din +din nc hdmp-1514 top view 0.47 ? 0.01 ? 0.1 ? 0.1 ? 0.1 ? lolb lola -por en_cdet +5.0 v lunuse +5.0 v rbc1 rbc0 com_det -lin +lin +5.0 v 0.1 ? nc ewrap -lck_ref
figure 21. typical receiver pin terminations for applications using high speed fiber links ( din). for 1062.5 mbd operation only, spdsel (pin 71) set high, non ping-pong mode (ppsel = 0). www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies, inc. obsoletes 5963-3353e 5964-6637e (11/99) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 +5.0 v rx[00] rx[01] rx[02] rx[03] rx[04] rx[05] rx[06] rx[07] rx[08] rx[09] rx[10] rx[11] rx[12] rx[13] rx[14] rx[15] rx[16] rx[17] rx[18] rx[19] refclk nc nc -din +din nc HDMP-1512 fig 21 hdmp-1514 top view 0.47 ? 0.01 ? 0.1 ? 0.1 ? 0.1 ? lolb lola -por en_cdet +5.0 v +5.0 v rbc1 rbc0 com_det -lin +lin +5.0 v 0.1 ? nc ewrap -lck_ref

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